[rdrdss23]

I've heard that the whole quantum tunneling stuff is in practical terms bullshit. While it's a real effect (and physicists looove to talk about it), it's virtually irrelevant b/c the overwhelming issues is parasitic capacitances. When you have a 3Ghz clocks, everything acts like a capacitor and you have current leaking all over the place (the smaller the circuit the closer all the elements are).

So transistors in modern processors don't end up switching consistently. There is all sorts of error correction to compensate for that, but it only goes so far.

[sigterm]

The gate leakage current was a serious concern until the High-K gate dielectric was found. It increased the gate dielectric thickness so tunneling current is reduced significantly (exponentially). Nowadays the main problems are subthreshold leakage and dynamic power. Here's a good article about it:

http://spectrum.ieee.org/semiconductors/design/the-highk-sol...

[rphlx]

> the main problems are subthreshold leakage and dynamic power.

This is exactly correct. Even at 28nm, many SoCs are intentionally using less than the max manufacturable transistor density, due to dynamic power/thermal constraints.

SRAM is scaling poorly too. It makes up 50-60% of many SoC designs yet at 1500MHz+ its density (Mb/mm^2) looks likely to increase just 1.1X between 28nm and 16nm.

Desktop CPUs are not going to get 32MB on-die caches any time soon. At least not without eDRAM.

[yvdriess]

On the other hand, I heard just this week at imec that currently 30% of the leakage is due to quantum tunneling. Nothing to sneeze at.