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by kazagistar 4694 days ago
Is there any plans to work hardware transactional memory into the mix?
1 comments
kingkilr 4694 days ago
Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.
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4buser 4694 days ago
Even new Intel Haswell's STM?
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sanxiyn 4694 days ago
Yes, Intel TSX too has a limited transaction size.
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