Hacker News new | ask | show | jobs
by kingkilr 4694 days ago
Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.
1 comments
4buser 4694 days ago
Even new Intel Haswell's STM?
link
sanxiyn 4694 days ago
Yes, Intel TSX too has a limited transaction size.
link