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Update on STM (morepypy.blogspot.com)
138 points by wisesage5001 4694 days ago
2 comments
nn4 4694 days ago
Obligatory anti STM hype links:

http://queue.acm.org/detail.cfm?id=1454466 http://webcache.googleusercontent.com/search?q=cache:HhZcU_j...

Pretty much all the generalized (not functional) memory TM schemes with adequate performance rely on hardware acceleration. If your design doesn't support that your design is wrong.

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kazagistar 4694 days ago
Is there any plans to work hardware transactional memory into the mix?
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kingkilr 4694 days ago
Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.
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4buser 4694 days ago
Even new Intel Haswell's STM?
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sanxiyn 4694 days ago
Yes, Intel TSX too has a limited transaction size.
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