[tjdetwiler]

ARM instructions are 32 bit, so there is a problem when you want to load a 32 bit literal. The assembler will get around this by sticking literals in the text section and then fixup the load with the correct offset.

Example, using a simple input:

  .globl _start
  _start:
    ldr r0, =0x20200000

Disassembles to:

  .globl _start
  _start:
    ldr r0, [pc, #-4]
    .word 0x20200000

[joosters]

Not a MOV and an ADD?

[tjdetwiler]

You can use that method (arm usually uses a "mov" and "movt" to load upper and lower half-words), but you would be using 2 instructions to accomplish the same thing that ldr with a literal pool does in one.

[joosters]

Not sure about a MOVT (my ARM assembler is only current to an ARM2...) but it's two (pipelined) instructions vs one instruction and a slow memory access. But then again, I'm thinking of a previous era with no instruction or data caches !

[tjdetwiler]

I speak mostly from an ARMv7 perspective (so pipelines, caches, prefetchers, etc are par for the course).

Your literal pool has a high degree of spacial locality WRT the instruction that references it. You can take measures to optimize this (see the ltorg directive) making I$ hits very likely.

In the end, the assembler is free to pick and choose which method is best for the target CPU and input code.