[joosters]

Not sure about a MOVT (my ARM assembler is only current to an ARM2...) but it's two (pipelined) instructions vs one instruction and a slow memory access. But then again, I'm thinking of a previous era with no instruction or data caches !

[tjdetwiler]

I speak mostly from an ARMv7 perspective (so pipelines, caches, prefetchers, etc are par for the course).

Your literal pool has a high degree of spacial locality WRT the instruction that references it. You can take measures to optimize this (see the ltorg directive) making I$ hits very likely.

In the end, the assembler is free to pick and choose which method is best for the target CPU and input code.