[zrobotics]

This is extremely cool, I've played with FPGA design but never really even looked into custom ASIC design due to budget concerns. I hadn't heard of the tinytapeout project. Any recommended links for getting started?

I have a (really dumb, kinda meme-y) project involving a dead hakko soldering iron and "Internet of Soldering", a custom ASIC for the actual front-end would be the appropriate level of silly and possibly could fit in the project budget.

[random__duck]

As the designer of "an ethernet connected beacon that counts and never overflows until the heat death of the universe" (https://talesonthewire.com/projects/until_heat_death_do_us_p...) I believe you have found the perfect audience for a memeish hardware project. So don't expect anything but my upmost support. :)

I detailed the roadmap for custom ASIC design a bit here: https://talesonthewire.com/projects/two_weeks_until_tapeout/... and joining the Tiny Tapeout discord community is a great place to reach out for help.

[toast0]

> So for everyone else also running multiple instances of experimental hardware on their local network I have added an additional 2 Byte magic number using the all so original 0xCAFE (little endian) allowing packet parsers to distinguish between this ASIC’s experimental traffic and your other experimental traffic.

Just saying, it's good form to do network stuff in big endian. Although since it's already done I dunno how hard you should work to retcon that to 0xFECA...

[inigyou]

If your 0xCAFE gives you a 0xFECA1A55, stop going there...

[toast0]

Last time I eat vegetables..

[zrobotics]

Thanks for the pointers, hopefully I get some time to get started in that project soon!

Although I should point out that you missed the opportunity tor making the world's slowest counter and avoiding needing any expensive memory. Just declock it to an extreme degree. Hard to debug a design that never outputs anything for literal eons though.

[Dylan16807]

You could easily drop the clock to 32kHz but that only saves 10 bits out of nearly 400. Getting to 1Hz requires increasing amounts of analog circuitry and only saves 26 bits. Going many powers of 2 slower starts to require counters inside your clock, so now you're replacing expensive integrated bits with much more expensive discrete logic bits.

So, since clocking low can't save you many bits, might as well give it enough bits to handle any clock up to the limits of your transistors.

[imtringued]

The tiny tapeout project doesn't really fix the economics either. There's the obvious IO bottleneck, but worse than that, a 1000 LUT FPGA fits bigger designs and costs almost nothing. Like $2.50/FPGA at 1000 units.

[inigyou]

Tiny Tapeout has its own guide for getting started