[mallets]

The really intriguing part is the "Custom ADC" here, seems like some kind of 1-bit ΣΔ oversampling ADC (704 MSPS?). Single differential transistor, and captured by FPGAs LVDS RX.

Neat way to reduce cost and pin-count? But I think the typical FPGA clock tree has poor jitter performance. Not using the internal PLL(s) might help with spurs but the clock buffers are unavoidable.

The documentation mentions it's likely further degraded by noise from switching regulators. Oh the joys of hunting RF noise sources.

[mrtnmcc]

We've got the switching noise nailed down. Fortunately the LVDS jitter doesn't affect the sigma delta too badly because that impacts proportional to baseband frequency which is largely filtered out by the decimation filters beyond 40 MHz.. With a total of eight ADCs per QuadRF, you can see we are getting huge savings by being custom! While the per-ADC ENOB is 7-8 bits, another nice thing about phased arrays is that the quantization/ADC noise averages away between elements, so with 8 ADCs in QuadRF we pick up another 1.5 bit giving 8.5-9.5 ENOB, which is frankly better than most SDRs. For the bigger phased arrays that improves further quickly.

[andrewstuart2]

I like to think of myself as pretty well-versed when it comes to hardware and software and even some RF. But this conversation has me hitting search a lot, lol. It's fascinating reading experts talk about a domain I have less experience in.

[geerlingguy]

Heh, welcome to RF; there are more rabbit holes to go down in domain specialty than I think there are grains of sand on a beach. I've gone down like... two. And I'm pretty overwhelmed.

I think that's why a lot of EEs and developers wind up getting an amateur radio license, or at least running a few fun RF projects.

[quietfox]

Glad I’m not the only one. I’ve been tinkering with sensors, robotics, sdr and similar stuff for 20 years now, but this conversation was way over my head.

[tverbeure]

That’s so cool!

Reading these comments first, I assumed you were using a variant of Spartan 6 LVDS TDC trick which allows up to 200 Msps rates. (https://sps.ewi.tudelft.nl/pubs/Homulle15fpga.pdf)

But this is a really interesting use case as well, and something that could be used for a 16 channel logic analyzer with analog recording support like the Saleae Logic 16 Pro, but without expensive ADC from Analog Devices.

[mallets]

Yeah, jitter doesn't matter too much at low frequency IF. I/Q calibration is more likely to be the bottleneck. That and close-in spurs from the fractional PLLs.

I have very little experience with MIMO / phased-arrays, this application likely doesn't need ultra high SFDR.

[mrtnmcc]

Yes, I actually designed the I/Q calibration for many of Analog Device's transceivers (AD93x), and indeed it is a fun problem. If you're interested in what was done for QuadRF, you can read: https://QuadRF.com/cals/txqec.html (Warning: Math!)

[mallets]

Oh wow, the AD936x series was impressive for its I/Q calibration. Still is I guess, because there's been no compelling alternative even a decade later.

As I mostly deal with single channel applications, I get to use double superhet and avoid runtime calibration. Not an option here, Zero-IF has too much in the Pros column for multichannel.

[mrtnmcc]

Yes once you have runtime IQ compensation figured out in digital, its essentially free and easily puts your image rejection ratio into the -50 to -60dBc range. I don't have a write up on the RxQEC, but it's rather trivial: you periodically compute the 2x2 IQ correlation matrix, then take the sqrt (e.g., Cholesky) and multiply your incoming Rx samples by that inverse. You can extend that further for widerband by using FIR taps but here the baseband matching is good enough to go with "single tap"

[Eisenstein]

For those confused about what this means, my understanding is this: when quantizing a wave you can use sampling rate to derive missing bits, so using even one bit can work if you do it fast enough, but jitter is a problem because it means the clock doesn't cleanly sync and it doesn't help non-quantization noise like those generated from switching supplies. Corrections welcome.

[mrtnmcc]

A good tutorial on sigma delta is https://www.analog.com/en/resources/technical-articles/sigma...

For a deeper dive, check out any of Richard Schreier's lectures.