[buran77]

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible.

Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.

What they actually deliver is a "nanostack architecture" built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip.

It's an impressive achievement nonetheless but it looks like the industry has a few too many marketers.

[adrian_b]

As it can be seen from the photos, horizontally the features are much bigger than 5 nm.

For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.

The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.

The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer, but that does not matter directly for the circuit density.

The supposed node size refers to horizontal dimensions, not to vertical dimensions.

Vertical dimensions of around 1 nanometer or less could be achieved already many decades ago, because they depend on growth speed and on time, not on lithography, like the horizontal dimensions.

The industry should have stopped decades ago to talk about the "size" but they should have characterized a CMOS process by its density, e.g. in logic gates per square mm.

However, an actual concrete number would be disliked by marketing, because they could no longer claim that their "1 nm" process is better than the "2 nm" process of another vendor, if their density is not really better.

[gabrielhidasy]

Just get better marketers to say your 2nm process has more gates per sqmm than your competition 1nm process.

[kailden]

Exactly. WatsonX AI quantum angstroms for e-business.

[quantum_state]

At some point, people would not know if they have the deal or not have the deal in this new era of quantum e-business ...

[xattt]

Now with Tivoli Monitoring!

[scythe]

The scale bar on the far right "photo" (micrograph?) doesn't make sense. It is only slightly less than half the scale bar on the middle photo (10 nm), but the image is clearly scaled up by much more than 2x. Individual silicon atoms are circled in the right photo, but the covalent radius of silicon is about 0.11 nm, so they should be much smaller if the scale bar is accurate.

[u1hcw9nx]

Unlike marketing terms, "nm density" is actually useful measure.

It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

[measurablefunc]

Density is mass per volume so how are you comparing it to a planar transistor? Your units don't even match.

[gruez]

Not all densities is mass per volume. eg. population density.

[measurablefunc]

It's a physical quantity per some unit of spatial measurement so the units still don't match up b/c in one case the transistors are stacked per volume & in the other case per area.

> Historically, "node" sizes (like 28nm or 7nm) directly correlated to the physical length of a transistor's gate. Today, names like 3nm or 2nm reflect a marketing generation. The actual transistors are significantly larger than these nanometer labels, meaning density varies between companies

> Research organizations like IEEE have proposed new metrics, such as transistors per cubic millimeter (MTr/mm^3), to accurately map future 3D scaling. However, commercial chip foundries resist this change because it would make it harder to calculate commercial yields and thermal density limits using standard industry formulas.

https://share.google/aimode/Z5BqUjlZWFNphm6Z6

[formerly_proven]

> It's a physical quantity per some unit of spatial measurement so the units still don't match up b/c in one case the transistors are stacked per volume & in the other case per area.

"Planar" and "3D" in this context refers to the shape of the transistors themselves. In a planar transistor the functional structure is spread out in the area, like this: https://en.wikipedia.org/wiki/File:MOSFET_functioning_body.s... while 3D transistors spread into the volume: https://en.wikipedia.org/wiki/Multigate_device#/media/File:D...

However the active devices are still just one layer. This isn't like 3D NAND where you actually have transistors on top of each other. So the comparison only considers the area for both kinds of transistors.

[measurablefunc]

In any case, I got the answer from the AI I was looking for & it makes sense. You can try to map the volumetric density to areal density but the mapping is not canonical so it doesn't say anything about the physical reality of actual transistor density since the reality is that it is a volumetric measure that gets fudged for marketing purposes.

[john_strinlai]

density is quantity per unit measure.

mass per volume is one example.

[amirhirsch]

Density is this reply.

[bronson]

https://en.wikipedia.org/wiki/Transistor_count#Transistor_de...

[jayd16]

Why not use something absolute, like nand-gates per volume?

[u1hcw9nx]

Transistor density in units of MTr/mm. (Million Transistors per square mm) is also used. The formula is

MTr/mm = 0.6×(NAND2 Tr Count)/(NAND2 Cell Area) + 0.4×(Scan Flip Flop Tr Count)/(Scan Flip Flop Cell Area)

[mikepurvis]

I am not a chip designer, doesn't area matter way more than volume? Vertical space is basically free; it's horizontal space that is at a huge premium.

[Smalltalker-80]

Yeah, the actual sizes are right there in the pictures, and never < 1 nm.

[Legend2440]

It's been decades since published node sizes had any connection to actual feature size. Sadly this is just how it works in the semiconductor industry now.

[amelius]

Who started it?

[lizknope]

https://www.eejournal.com/article/no-more-nanometers/

Sometime around 2011 when Intel named their process node 22nm which the gate length was 26nm

[Legend2440]

Your article says it started earlier:

>So essentially, since 1997, the node name has not been a representation of any actual dimension on the chip, and it has erred in both directions by almost a factor of 2.

[roelmore]

Smart money would be on the first person who realized that the expertise required to understand the technical details had grown beyond that possessed by 51%+ of stock investing (trading?) population as weighted by transaction volume.

[pseudosavant]

My read on it was that they are trying to imply a transistor density (in a 2D plane sense) that is comparable to a 1nm process? But they achieve that through stacking (3D, not 2D) since the features aren't actually anywhere near 1nm?

[makeitdouble]

If they're adding a dimension, the marketing should reflect that.

I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"

[y1n0]

“TeraThread”

[ktm5j]

What industry doesn't have a few too many marketers? Take everything with a grain of salt.

[somesortofthing]

only a matter of time before some marketer figures out they can get promoted by branding a generation of chips 0nm

[roflmaostc]

yeah, where on the pictures is the 0.7nm feature? The linespacing is around 5nm. Is it the white line which is 0.7nm?

[TallGuyShort]

I really can't see where the 0.7nm is coming from. The white line looks like it's just an edge of a feature that is "15 rows of silicon atoms", which by some quick arithmetic on Wolfram Alpha has to be AT LEAST ~1.6nm, and the way the rows of atoms appear to be packed in that image and by the provided scale, it seems to be significantly more. Using the white line as a meaningful measurement seems to me to be more misleading than any other interpretation here.

[wmf]

It's the equivalent performance of a 0.7 nm planar transistor. It's not about the feature size.

[adrian_b]

A 0.7 nm planar transistor made of silicon has no performance, because a device so small cannot function as a transistor.

The intended meaning of "0.7 nm" is that if you compare the transistor density per area of a "0.7 nm" manufacturing process with that of a "350 nm" process (like used for some Pentium II CPUs, at a time when "350 nm" was a real length), the ratio between the transistor densities is (350 nm / 0.7 nm)^2 = 500^2 = 250,000.

Comparing with the number of transistors of a Pentium II, a 0.7 nm CPU should be able to contain about 5000 billion transistors. This is consistent with the fact that the latest 3 nm NVIDIA Rubin GPU has 336 billion transistors and a 0.7 nm circuit must have a density around 16 times greater than a 3 nm circuit.

However, for many of the modern node names used by some companies even this computation is not really true, because marketing may have chosen an arbitrary name that is smaller than for the last process of the main competitor.

For now, IBM has not provided any kind of information that could prove their claim that their new CMOS process has the transistor density corresponding to "0.7 nm" (i.e. 16 times greater than the TSMC "3 nm" CMOS process).

[api]

Better metrics are transistors/mm^2, performance/watt, and raw performance, since at this point "nm" is fluff and easily game-able.

Different companies measure it differently too. This was a while ago, but I remember reading that Intel 10nm was more or less close to TSMC 7nm. I'm sure this is still true to varying degrees.

[cyanydeez]

On the otherhand, no investor really cares what it's called, they just need to know it's next gen.

[formerly_proven]

> Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.

We care about PPA (power, performance, area) and not how large or not-large features actually are. Comparing gate lengths between a 1980s planar transistor and a 2010s 3D FinFET or GAA transistor is obviously nonsense, the relatively aligned node names of the industry actually do make sense as a shortcut here.

[colechristensen]

You have to admit it's getting progressively sillier though.