Super cool work. I love seeing this direction taken all the way to hardware.
I'm a big fan of KANs. The really seem like the start of something big and new. We've got a couple of papers out and in the works on KANs. The most relevant to OP's is this one: https://arxiv.org/abs/2512.15742v2
Searching around github and found someone has put up a github repo with a Julia implementation of the article here including FPGA implementation of a KAN MNIST classifier in Verilog. https://github.com/philtomson/KAN_LUT