[kens]

That's basically the RISC approach, using simple one-clock instructions instead of complex microcoded instructions. In the case of the 8087, it made sense to use microcode because the 8087 is running in parallel with the regular 8086 processor. If the 8087 is constantly fetching micro-instructions from RAM, it will get in the way of the 8086. (Note that RISC chips rapidly added floating-point units, even though that goes against the strict RISC ideology.)

[userbinator]

This is also why RISC would never have happened if it weren't for the fact that, for a brief period in the history of computing, RAM was faster than the core. Single-cycle instructions only make sense if the fetch can keep up.

[cyberax]

I don't think this is correct? You can certainly fetch more than one cycle's worth of data each cycle even on modern RAM.

It's a question of throughput that can be extended cheaply enough.

[gblargg]

I'm reading that L1 takes 4-5 cycles to read on modern CPUs, whereas it was just one cycle in the late 1980s.

[userbinator]

I was referring to the 80s when RISCs were first invented.

[mysterion1]

Judging by the register area bit density, it seems it would have space for 3-5kbit SRAM cache (replacing the 26,368 bit ROM). I wonder if the basic 4 ops+some approximation functions like sqrt would fit in there. Purely alternative history ;)