[userbinator]

This is also why RISC would never have happened if it weren't for the fact that, for a brief period in the history of computing, RAM was faster than the core. Single-cycle instructions only make sense if the fetch can keep up.

[cyberax]

I don't think this is correct? You can certainly fetch more than one cycle's worth of data each cycle even on modern RAM.

It's a question of throughput that can be extended cheaply enough.

[gblargg]

I'm reading that L1 takes 4-5 cycles to read on modern CPUs, whereas it was just one cycle in the late 1980s.

[userbinator]

I was referring to the 80s when RISCs were first invented.