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by benj111
25 days ago
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This looks interesting. I've been thinking along somewhat similar lines of a C but instead of a PDP 11 as the virtual machine, why not risc V. Could of questions. Do variables as registers get enforced at all? If you're going to have any type of function you need to that the first arg goes in the right place. Second. One risc V instruction doesn't necessarily mean one risc V instruction. So I don't think you should be holding yourself to the same standard. This then makes while loops possible and easier to read if statements. For me the benefit of something like this is knowing what is happening under the hood. I don't need to know that a statement will translate to one instruction, just that I understand what instructions it will actually expand to. |
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For your second point, yes, RISC-V assemblers sometimes transform written assembly into their equivalent instructions (e.g., 'mv foo, bar' becomes 'addi foo, bar, 0'). Riscrithm uses normal RISC-V syntax (like 'ret' or 'nop' keywords rather than the true on-metal command). This doesn’t mean we lose assembly’s flexibility—commands are always as close to the metal as possible. Keywords like 'swap' of course expand into more lines of code, but these are always clear expansions the developer can understand and verify anytime. The goal of Riscrithm is to make writing assembly simpler and cleaner, which is why I focus on mapping instructions clearly to their true on-metal equivalents. If you want to see which instructions expand into what, you can check the Developer Manual, which now includes four Riscrithm v1.1 examples with their corresponding assembly. Again, great points and comments—I really appreciate them!