[pjdesno]

Flash went from within 2x the price of DRAM in 2012 or so to maybe 40-50x cheaper today, driven somewhat by shrinking feature sizes, but mostly by the shift from SLC (1 bit/cell) to TLC (3 bits) and QLC (4 bits) and from planar to 300+ layer 3D flash.

Flash is near the end of the “S-curve” of those technologies being rolled out.

During that time HDD technology was pretty stagnant, with a mere 2x increase due to higher platter count with the use of helium.

New HDD technologies (HAMR) are just starting their rollout, promising major improvements in $/GB over the next few years as they roll out.

You can’t just look at a price curve on a graph and predict where it’s going to go. The actual technologies responsible for that curve matter.

[Dylan16807]

> mostly by the shift from SLC (1 bit/cell) to TLC (3 bits) and QLC (4 bits) and from planar to 300+ layer 3D flash

That "and" is doing a lot of work.

In 2012 most flash was MLC.

In 2025 most flash is TLC.

> During that time HDD technology was pretty stagnant, with a mere 2x increase due to higher platter count with the use of helium.

They've advanced slower than SSDs but it wasn't that slow. Between 2012 and 2025, excluding HAMR, sizes have improved from 4TB to 24TB and prices at the low end have improved from $50/TB to $12/TB.

[Dylan16807]

This is one of those times a downvote confuses me. I corrected some numbers. Was I accidentally rude? If I made a mistake on the numbers please give the right numbers.

If my first line was unclear: We might say the denser bits give us a 65% density improvement. And quick math shows that a 80-100x improvement is actually nine 65% improvements in a row. So the denser bits per cell aren't doing much, it's pretty much all process improvement.

[pjdesno]

It’s mostly 3D, not process.

3D flash is over 300 layers now. The size of a single 300-bit stack on the surface of the chip is bigger than an old planar cell, but that 300x does a lot more than make up for it.

3D NAND isn’t a “process improvement” - it’s a fundamental new architecture. It’s radically cheaper because it’s a set of really cheap steps to make all 300+ layers, not using any of the really expensive lithography systems in the fab, then a single (really complicated) set of steps to drill holes through the layers for the bit stacks and coat the insides of the holes. Chip cost basically = the depreciation of the fab investment during the time a chip spends in the fab, so 3D NAND is a huge win. (just stacking layers by running the chip through the process N times wouldn’t save any money, and would probably just decrease yields)

A total guess - 2x more expensive for extra steps, bit stacks take 4x more area than planar cells, 300 layer would have 300/8 = 37.5x cheaper bits. (That 4x is pulling a lot of weight - for all I know it might be more like 8x, but the point stands)

[Dylan16807]

I was counting all the 3D manufacturing innovations as "process improvement". I'm not sure why you don't.

Anyway the point stands that bits per cell is barely doing anything compared to making the cells cheaper.

[pjdesno]

Because they made something different with the same process, instead of making the same thing with a different process. Feature size didn’t get any smaller. (or, rather, you get the order of magnitude improvement without it, and those gains were vastly more than the feature size improvements over that time period)

Also because “process improvement” usually refers to things where you get incremental improvements basically for free as each new generation of fab rolls out. Unless you can invent a 4D flash, this is a single (huge) improvement that’s mostly played out.

[Dylan16807]

> with the same process

Same process node.

Node is part of process, but all the layering and etching techniques they figured out to make 3D cells are also process. At least that's how I see it.

Oh well, I don't want to argue definitions, I just want to clarify what I meant.

[pjdesno]

Oh, and no one has a solution to make HDDs faster. If anything, they may have gotten slower as they get optimized for capacity instead of speed.

(Well, peak data transfer rate keeps going up as bits get packed tighter, but capacity goes up linearly with areal bit density, while the speed the bits go under the head goes up with the square root.)

(Well, sort of. For a while a lot of the progress came from making the bits skinnier but not much shorter, so transfer rates didn’t go up that much)