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by pjdesno
272 days ago
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It’s mostly 3D, not process. 3D flash is over 300 layers now. The size of a single 300-bit stack on the surface of the chip is bigger than an old planar cell, but that 300x does a lot more than make up for it. 3D NAND isn’t a “process improvement” - it’s a fundamental new architecture. It’s radically cheaper because it’s a set of really cheap steps to make all 300+ layers, not using any of the really expensive lithography systems in the fab, then a single (really complicated) set of steps to drill holes through the layers for the bit stacks and coat the insides of the holes.
Chip cost basically = the depreciation of the fab investment during the time a chip spends in the fab, so 3D NAND is a huge win. (just stacking layers by running the chip through the process N times wouldn’t save any money, and would probably just decrease yields) A total guess - 2x more expensive for extra steps, bit stacks take 4x more area than planar cells, 300 layer would have 300/8 = 37.5x cheaper bits. (That 4x is pulling a lot of weight - for all I know it might be more like 8x, but the point stands) |
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Anyway the point stands that bits per cell is barely doing anything compared to making the cells cheaper.