[bangaladore]

This motherboard already supports PCIE 5.0 for NVME, so it's likely the board stack up is plenty sufficient for PCIE 5.0.

The differential impedance is also identical for PCIE 4.0/5.0 so again, likely not a physical difference issue.

Which basically suggests that the routed the 4.0 lanes much sloppier than 5.0.

[Aurornis]

It’s not that simple. You could get PCIe 5.0 working on the cheapest FR-4 board if you kept trace lengths short enough.

The trace lengths matter a lot, among other things. You can’t draw conclusions like this.

[bangaladore]

The general advice is 5 mils Intra-Pair and no specific requirement for Inter-Pair. These follow the same engineering guidelines as PCIe 4.0, with identical impedance and coupling. As far as I can tell, there are no significant differences, aside from PCIe 5.0 having smaller theoretical margins. Even then, the 5 mils spec is likely overkill for both.

From what I’ve read, a well-designed PCB that supports PCIe 4.0 should also meet PCIe 5.0 requirements electrically and for signaling. I suspect the issue may be related more to power delivery or EMC than to trace layout or stack-up. Alternatively, it could just be an AMD policy decision to limit PCIe 5.0 support on this chipset variant, rather than a design flaw.

[toast0]

> I suspect the issue may be related more to power delivery or EMC than to trace layout or stack-up.

Power delivery shouldn't be an issue, the slot power limits haven't changed afaik, max is 75W for an x16 card since the beginning.