It is aimed at a completely different market from RISC-V.
RISC-V advantages is that it is an incredible simple and extensible architecture aimed at low power / embedded use cases. It is also easy to customize (similar to ARM) for specific use cases.
Power ISA is a super computer chip, while RISC-like, has a lot of legacy baggage and isn't designed for low-power nor is it designed for embedded situations. It also is not designed for customizability, it is more like a monolith project.
Power ISA will have space at the top of the market for very high performance CPUs. But I think it will be stuck there as there are no benefits over RISC-V in the areas where RISC-V is growing right now.
That isn’t actually true. I‘ve personally worked on an embedded POWER processor https://github.com/electronicvisions/nux. It is used as a dual core embedded micro-controller in a neuromorphic chip. Each core has just 16kB of memory on chip and 4kB instruction cache. POWER has subsets of the instruction set which have a gcc and llvm target and are well suited for embedded use cases.
Main advantage of RISCV at this point is that it has a larger community. But at the time it didn’t even have a vector instruction set, whereas we could easily modify the POWER one for our purposes.
RISC-V is absolutely not and never has been 'aimed at low power / embedded'. Literally from the very beginning the target was 'be an ISA for everything'. Its just natural that simpler things were standardized first and came to market first.
That POWER is better at top of the market is highly questionable, every new startup coming into the high performance space has universally picked RISC-V over OpenPOWER.
Also, nowadays even complex ISA were fine for embedded. The cost difference for stuff like that is tiny. Its really just about how many options do you have in the market, both open and closed. And that's where RISC-V by now simply has more.
OpenPOWER was only fake open for a long time, while marketing itself as open. Only when they were totally getting crushed, did they update and are more like RISC-V, but it was many years to late.
Power ISA absolutely was used in embedded contexts for years. Decades even.
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Instruction sets aren't very important actually. Like yeah, compiler infrastructure helps but a lot of embedded decision making is about peripherals.
PowerQUICC had powerful and extendable I/O that could be customized to many different needs. And I believe the bulk of those benefits stay over to the updated ARM chip QorIQ (as NXP bought FreeScale and seems to have prioritized ARM).
After Motorola has abandoned totally (MC88k, M.core) or partially (MC68k => Coldfire) its older ISAs and it has transitioned to using the POWER/PowerPC ISA, it has applied it to the market in which they was interested, designing many kinds of microcontrollers with it, mainly for the automotive and communications markets, where microcontrollers with higher performance were required. Around the same time IBM has also introduced a series of microcontrollers based on the POWER ISA (PowerPC 4xx).
However, when the POWER ISA has initially been designed, before its launch in 1990, its target were high-end scientific workstations and servers made by IBM. The idea of using it in embedded computers has come much later, when the increased density achievable in integrated circuits has made that possible.
Sure. But the embedded PowerQUICC chips were in use between the years 199x and 201x, and are still manufactured today in 2025.
My overall point is that Power ISA has a long history as both high performance compute AND embedded (be it industrial, automotive, or space embedded).
Maybe in the late 1980s POWER was high performance only. But there's a big history here and it's weird to see this discussion ignore Power ISA's long embedded history.
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Does OpenPower have a chance today? I dunno. Obviously the hype is in RISC-V and maybe a bit of ARM. But it's not a bad ISA and Power used to target embedded not very long ago
RISC-V has obviously been initially designed with the only purpose of being extremely simple to implement, simple enough to be implementable by students.
Nothing else can justify the weird choices made in designing RISC-V.
The idea to use RISC-V in actually useful devices must have come only after the initial design and for this purpose the only advantage of RISC-V versus designing some proprietary CPU core is that for RISC-V there already exists a significant amount of tools for software development, i.e. linkers, assemblers, compilers, debuggers, a few optimized libraries etc.
This advantage of RISC-V is extremely important, because developing compilers and all the other required software tools for any new ISA requires much more work and resources than the hardware design of a CPU core implementing it.
However, it is sad that the first ISA with a permissive license allowing it to be used by everyone everywhere has been one so bad as RISC-V.
It is absurd to claim that the target of RISC-V is to 'be an ISA for everything', when it does not even have adequate means for detecting integer overflow, a feature that existed even in much smaller ancient 8-bit microprocessors, like Motorola MC6800 (1974) and Zilog Z80 (1976).
Startups choose RISC-V because it is a fashionable buzzword good for pleasing possible investors and because their team does not include anyone with experience in low-level assembly programming or compiler back-end implementation, the only people who can assess the quality of an ISA.
The reasoning for this choice in the base ISA is discussed in the RISCV ISA manual, Section 2.4 on "Integer Computational Instructions" [1]. Given that RISCV is a modular ISA, it should be possible in principle to have suitable ISA extensions that do integer overflow detection.
Maybe the absence of such an extension in 2025 indicates that this is not a pressing need for many RISC-V users?
While very convenient to quickly link some ancient draft spec, let's try and stick to the actual ratified specifications[0].
Of course, the rationale is still there in section 2.4 of the current (20250508) ratified version of The RISC-V Instruction Set Manual Volume I: Unprivileged ISA.
You should learn about the history of RISC-V. RISC-V was initially designed to do research on advanced instructions architectures, like Vectors. So writing 64 bit chips with large vector engines was literally the initial design goal. And they deliberately went threw all historical bad ideas that were known to cause issues in out-of-order designs because the knew they wanted to do research on that as well. So its quite simply a historically well documented fact.
But they needed a simple base ISA that they could extend in different ways because different people planned on doing different kind of research on top.
When they then realized their was a need for a permissive license ISA that would be used be people outside of Berkley, like that they formulated a clear goal that is in all their early presentations, and it was "be the ISA for everything".
> when it does not even have adequate means for detecting integer overflow
Seems adequate for 1000s of companies who use RISC-V.
There are pros and cons of not having it, and the argument that 'X other design had feature Y' isn't an actual argument. Nobody has ever denied that they could have added that, its simply because they didn't want to.
> because it is a fashionable buzzword
I'm sure you are so much smarter then Jim Keller and David Dizel ...
I feel like regardless of what you can accomplish with it will be drowned by having to deal with IBM's brilliant handling of their products.
The only occasions I interacted with POWER was in projects where the client was happily deploying bog standard enterprise amd64 servers running Linux to replace it.
>You can accomplish the same task in substantially fewer instructions, leading to higher performance for a given level of design effort.
The statement is true and favorable to RISC-V, as it is the one with lowest instruction count and code size; RISC-V wins, and it is not even close.
>Also a more developed software ecosystem.
Historically true, but right now the momentum is with RISC-V, and it is absolutely is catching up, and no longer a point of contention.
e.g. Debian is the largest Linux distribution by its library of packaged software. There, RISC-V has already overtaken[0] it in available package count.
RISC-V advantages is that it is an incredible simple and extensible architecture aimed at low power / embedded use cases. It is also easy to customize (similar to ARM) for specific use cases.
Power ISA is a super computer chip, while RISC-like, has a lot of legacy baggage and isn't designed for low-power nor is it designed for embedded situations. It also is not designed for customizability, it is more like a monolith project.
Power ISA will have space at the top of the market for very high performance CPUs. But I think it will be stuck there as there are no benefits over RISC-V in the areas where RISC-V is growing right now.