[orbifold]

That isn’t actually true. I‘ve personally worked on an embedded POWER processor https://github.com/electronicvisions/nux. It is used as a dual core embedded micro-controller in a neuromorphic chip. Each core has just 16kB of memory on chip and 4kB instruction cache. POWER has subsets of the instruction set which have a gcc and llvm target and are well suited for embedded use cases.

Main advantage of RISCV at this point is that it has a larger community. But at the time it didn’t even have a vector instruction set, whereas we could easily modify the POWER one for our purposes.