[IshKebab]

This looks much more likely to succeed tbh. Similar enough to SV that you can piggy back off the features that you're likely never going to replicate (SVA, functional coverage, multiple clock domains, etc. etc.) but also fixes the footguns.

[dalance]

As the author of Veryl and an ASIC frontend engineer, I aim to enable smooth transitions from existing SystemVerilog projects, making it immediately applicable to ASIC projects. (In fact, it’s already being applied to an ASIC currently under design.) I see languages like Spade and SUS as HDLs for a slightly more future-oriented.