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user: dalance
created: 2024-03-14
karma: 16

submissions:

Veryl Simulator: Performance Comparison with Verilator
3 points | 0 comments
Veryl 0.20.0: logic synthesis and type inference are supported
2 points | 0 comments
Veryl 0.16.4 – A Modern HDL as Alternative to SystemVerilog
3 points | 0 comments
0 points | 0 comments
Veryl 0.16.0 – A Modern HDL as Alternative to SystemVerilog
3 points | 0 comments
Veryl 0.14.0 – A Modern HDL as Alternative to SystemVerilog
2 points | 0 comments
Rust Document Translation Project
1 points | 0 comments
Verylup 0.1.2 – the official installer for Veryl
1 points | 0 comments
Veryl 0.13.0 – A Modern HDL as Alternative to SystemVerilog
2 points | 0 comments
Veryl 0.12.0 – A New Hardware Description Language
1 points | 0 comments
Veryl v0.12.0: A New Hardware Description Language
1 points | 0 comments
0 points | 0 comments