[mattofak]

This sounds fun to play with and get feet wet in HDL, but it's only a lattice ice40, I have no idea what you'd seriously do with this. Usually ice40 are used as glue logic, or multiplexing/buffering a bunch of ADC/DAC chips so the processor can do large data transfers instead of a bunch of tiny ones.

The website claims hardware acceleration and... I doubt they got timing closure on the soft CPU at anything greater than 100MHz and you still have to get data to/from it at likely 30~40 MB/s via an SDMMC bus.

[mechagodzilla]

It's got 128KB of on-die SRAM - you could have a Z80 and a 6502, both with a full complement of SRAM!

[ruslan]

Lattice's FPGAs are very nice. With an iCE40 you can have a full featured RISC-V soft-core (RV32IMFAC) at some 80 MHz.

[wyager]

For a lot of the iCE40 chips, it's extremely difficult to reliably get fMax > 50MHz even with extremely aggressive pipelining. I assume 80MHz is only possible on the highest-speed parts in the iCE40 family

I switched a design from iCE40 to ECP5 and got a ~3x speedup "for free"

Agreed that using Lattice FPGAs is super nice, mostly because you get to use the open-source Yosys toolchain, which is vastly better than proprietary toolchains IMO

[Neywiny]

Agreed. Not enough processing power for anything onboard, no IO out the back (seems like a missed opportunity tbh) for expansion to do fun things. Not sure what I'd do with this.

A quick search shows Hirose has a 0.5mm tall FPC connector that could fit 25 contacts within the width. Looking at their pictures, they have some spare height (unsure if enough though) and depth to move components forward. Even with good grounding, idk 12 IO is a decent amount.