[jrk]

SRAM is scaling significantly more slowly than logic in recent process nodes.

[ericd]

Ahh that explains it, thanks. Seems like a potentially large problem given their strategy.

[phonon]

They could use something like GCRAM[1] to double capacity if they had to...but it's not clear how much worse performance would be.

[1]https://raaam-tech.com/products/

[nsteel]

The performance doesn't look great (yet). See Fig. 7

https://www.eng.biu.ac.il/fishale/files/2020/12/A-1-Mbit-Ful...

[phonon]

Cerebras runs at 1.1 GHz[1], and this was a much earlier design on 16nm so it might be a good fit by now. Their TSMC 5 nm version is scheduled for early 2025.[2]

[1]https://cerebras.ai/blog/cerebras-architecture-deep-dive-fir...

[2]https://www.eenewseurope.com/en/raaam-signs-lead-licensee-fo...

[nsteel]

They'd have to quadruple their performance to be relevant in the market generally, here's to hoping.

[phonon]

Yeah...but double density and 1/10 power consumption would be outstanding for ML type loads...hopefully they can get performance to at least the 1.x GHz range! I'm keeping an eye out...dollars to donuts Cerebras will be using this within a year, once it's qualified for TSMC 5nm.