Can someone explain why those differential pairs are routed with so many curves instead of straight paths? (E.g. see the photo under the “ADC and DAC rotting” section)
"The traces are length-matched with squiggly lines[...]. The trace matching requirement is ±10 ps according to the Zynq PCB design guide, which is approximately ±2mm in trace length. [...] There is also some delay difference inside the FPGA package which should be considered in the length matching."
This is a shortened excerpt from the article. It can be found below the image with six colorful images of PCB layers. I'm curious how the delays inside the FPGA package are known. Is there a table which pin adds how much delay to a signal or something like that?
The FPGA manufacturer has characterized all their package pin delays. It's possible to export a csv file with internal delays of the package for each pin from the FPGA design tool. With Xilinx Vivado it's just File -> Export I/O Ports.
No, it needs to be done manually. It wasn't as tedious as it sounds though. Most of the pins are very close in delay already and there were just few traces that I had to adjust a little.
This is a shortened excerpt from the article. It can be found below the image with six colorful images of PCB layers. I'm curious how the delays inside the FPGA package are known. Is there a table which pin adds how much delay to a signal or something like that?