[henrikf]

The FPGA manufacturer has characterized all their package pin delays. It's possible to export a csv file with internal delays of the package for each pin from the FPGA design tool. With Xilinx Vivado it's just File -> Export I/O Ports.

[_Microft]

Does KiCad allow to take these delays for each pin into account automatically or do you need to do all that manually?

Edit: it's using the pad property of "pad-to-die-length" if doing it manually, right?

[henrikf]

No, it needs to be done manually. It wasn't as tedious as it sounds though. Most of the pins are very close in delay already and there were just few traces that I had to adjust a little.

[mhh__]

How is kicad getting along with RF work in 2024, would you say?

I did some prototyping but never got the stage if actually fumbling around with PCBs a few years ago, things seemed to progressing quite well.