[Keyframe]

This is something I'm clueless about and can't really understand. They say this is 24kW hungry. How does CPU power consumption really work on electrical level, what warrants that much power, even for regular CPUs? Like, from the basics level.. is it resistance of the material with frequency of switching or what is really going on there? Where does the power go on such a relatively small surface?

edit: thanks people, makes sense now!

[magicalhippo]

Modern CPUs are built using CMOS MOSFET transistors[1]. The gate, which controls if the transistor conducts or not, is effectively a small capacitor. The gate capacitor has to be charged up for the transistor to conduct[2], ie you have to stuff some electrons into it to turn the transistor on.

Once you've done that, the transistor is on until the gate capacitor is discharged. This requires getting rid of the electrons you stuffed into it. The easiest is to just connect the gate to ground, essentially throwing the electrons away.

So for each time the transistor goes through an on-off cycle, you need to "spend" some electrons, which in turn need to be supplied from the power supply. Thus higher frequency means more current just from more on-off cycles per second.

There's also resistive losses and leakage currents and such.

Now in theory I suppose you could recycle some of these electrons (using a charge pump arrangement[3]), reducing the overall demand. But that would require relatively large capacitors, and on-chip capacitors take a lot of chip area which could have been used for many transistors instead.

[1]: https://en.wikipedia.org/wiki/CMOS

[2]: https://en.wikipedia.org/wiki/MOSFET#Modes_of_operation

[3]: https://en.wikipedia.org/wiki/Charge_pump

[Workaccount2]

It simply takes a non-zero amount of energy to turn a transistor on and off.

Add up trillions of transistors, flicking on and off billions of times a second, and you get enormous power draws.

What is actually drawing power is the gate capacitance of the transistors. If the transistor were a physical switch, the gate capacitance is the "weight" that must be put on the switch to flip it. Of course this weight gets smaller as the switches shrink and as the tech improves, but it will always be non-zero.

None of this accounts for resistive losses either, which is just the cost of doing business for a CPU.

[danbruc]

Yes, the power consumption comes from the resistance of the circuit. In case of CMOS circuits there would ideally be no current flow when no signal changes but transistors are not perfect and have leakage currents. When signals change, primarily triggered by the clock rising or falling, there is a short time in which the supply rail and ground rail are essentially shorted out.

Each gate has logically two transistors of which exactly one is always conducting, either connecting the output to the supply rail making the output a one, or connecting the output to the ground rail making the output a zero. When the output of the gate changes, both transistors have to switch in order to connect the output to the other rail than before. While this happens both transistors are conducting at the same time allowing current to flow from the supply rail to the ground rail.

In addition to that the input capacitances of subsequent gates get charged from the supply rail when the output goes high and discharged into the ground rail when input goes low. So every signal change pumps some charge from the supply rail through the input capacitances to the ground rail.

[Tuna-Fish]

delete

[bgnn]

This is completely wrong. I've desiged ICs from 350nm down to 3nm technology. I don't know what do you mean by transistors are biased. If you mean SOI body bissing, it's not a common technology.

Crowbar current is still a big problem. Leakage of Finfets are crazy, especially when you use ulvt devices, which you need for high performance.

The previous post is fully correct. Though the bulk of the power is switching capacitor.

[danbruc]

Does modern logic mean sub-threshold logic or does this apply generally?

[bgnn]

a lot of good answers. just couple points to add: - Charging a capacitor from 0 to Vdd volts takes E=CVdd^2 amount of energy. To find the power (energy/second) you need to multiply this with how frequently you do this, i.e. clock frequency. So, P=FCVdd^2. So most digitak circuits power scales linearly with frequency, and quadratically with power supply voltage Vdd.

- Half of themis power is resistive loses. This is kinda a fundamental thing. Charging a capacitor with a resistor is "lossy".

- Some of the charge is reused within the circuits