[zozbot234]

SRAM size has not been scaling at all in recent nodes, so these days the notion of uniform scaling is also breaking down quite a bit. This means that future designs will have less cache memory per core, unless they use chiplets to add more memory (either SRAM or eDRAM) close enough to the chip to become usable as some kind of bespoke cache.

[atq2119]

Just for the record, the "not at all" part is incorrect for the nodes I'm aware of. Correct would be "way worse", i.e. it's still getting denser, but the improvement is way worse than that of random logic.

[wtallis]

TSMC's N3E (their first 3nm that will actually see broad use) has the same SRAM cell size as N5. Their original 3nm had 5% smaller SRAM cell size than N5, but that turned out to be too aggressive and the process was too expensive for most of their customers. So for the time being, TSMC has indeed hit a wall for SRAM scaling. But it looks like N3P will be able to shrink SRAM again.

[bee_rider]

Hopefully we can get really widespread 2.5D packaging and just start including “oops all SRAM” layers.

[atq2119]

Thanks, I had missed that development.