[SeasonalEnnui]

I agree with what the parent is alluding to; the introduction of the RP1 is very understated but perhaps it's more interesting to SBC engineers rather than the end users.

In other words: 1. The RP1 (implemented on TSMC 40LP) contains all the power hungry/high bandwidth IO that is difficult to do on smaller process nodes. This allows the main processor to be moved to smaller nodes or even a different vendor/architecture in future boards. Easier to target better power efficiency in the future. 2. Going forwards, the IO feature set will now be consistent and reliable, by reusing RP1. It is no longer a requirement to try to get these peripherals on the main processor.

[bemusedthrow75]

Yes, it is this -- and what the sibling comment says.

It's clear that at least these things have changed:

1) there is now independence from the "old smartphone processor" model

Because the RP1 allows them to take control of the very bits of the puzzle that the Pi pioneered and apply them more broadly (including to x86 hardware if they chose to; they clearly did this in the development process)

2) nothing in particular stops them selling the RP1 as-is (except that they are not going to).

There have been some interesting allusions very recently as to what the success of the RP2040 and the RP1 might mean for a future microcontroller lineup, but my guess would be a mid-sized processor optimised for very small educational computers and emulating larger machines.

I would expect to see an RP2040 successor board based around something like the RP1 with USB-C and more concessions towards DVI/HDMI for one thing.

3) they now don't have all their eggs in the one basket (which is better for the foundation)

4) they could now choose a "partnership" model where something like the RP1 turns up in other people's hardware; there are already SBCs on the market using RP2040s for GPIO. [1,2]

Essentially, what has happened is not an incremental change. It's not even particularly incremental in the Pi 5, which is architecturally new.

It is a step change on the design level but also on the business level.

[1] https://www.tomshardware.com/news/thunderberry5-sbc-to-take-...

[2] https://linuxgizmos.com/low-profile-radxa-x2l-sbc-featuring-...

[paulmd]

I mean, you are fundamentally describing a chipset/southbridge. It is a common approach and it has tradeoffs (much lower efficiency than monolithic SOCs and additional data movement power).

It is an “interesting” choice for an SBC (probably a bad one given the lower efficiency and higher BOM cost) but overall it hasn’t changed the fact that the N100 is still a faster, cheaper, more efficient device (despite its monolithic SOC design!) unless you actually need the GPIO.

It’s really only an improvement vs the early RPi 1 boards where everything was interfaced using a 500mbps half-duplex usb2 connection as a system bus. That was an exceptionally bad design, particularly in the days when the (closed-source) kernel modules would drop usb frames under load. But the newer ones with sata support etc have already moved away from this.

It is more interesting that rpi is branching out into chip design etc, vs relying on third-party suppliers or pre-existing designs, than on an actual technical level.