[paulmd]

I mean, you are fundamentally describing a chipset/southbridge. It is a common approach and it has tradeoffs (much lower efficiency than monolithic SOCs and additional data movement power).

It is an “interesting” choice for an SBC (probably a bad one given the lower efficiency and higher BOM cost) but overall it hasn’t changed the fact that the N100 is still a faster, cheaper, more efficient device (despite its monolithic SOC design!) unless you actually need the GPIO.

It’s really only an improvement vs the early RPi 1 boards where everything was interfaced using a 500mbps half-duplex usb2 connection as a system bus. That was an exceptionally bad design, particularly in the days when the (closed-source) kernel modules would drop usb frames under load. But the newer ones with sata support etc have already moved away from this.

It is more interesting that rpi is branching out into chip design etc, vs relying on third-party suppliers or pre-existing designs, than on an actual technical level.