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RISC-V is becoming a worldwide interop standard, and a real one, namely royalty free and which will be stable in time once we get all the "now we know" features, and all that at the ISA level (x86_64 and ARM are _NOT_ worldwide royalty free). And don't be mistaken, there is no perfect ISA (it is said "average"), it does not exist, only a set of trade-offs and compromises which will not fit all use-cases perfectly. RISC-V is a US Berkley initiative. Have a look at wikipedia where you'll find most of the answers to your questions. That said, to be a success, RISC-V will need _extremely_ performant implementations all across the board ("embedded", desktop, server), micro-archs and silicium process. It will have to survive its mistakes: for instance critical bugs in its major micro-archs or design flaws (you have to presume it will happen). And without access to the best silicium process, it _WON'T_ have performant implementations. Because there is no "enough" in the silicium industry, it wants always more transistors and less power consumption, and each new silicium process brings significant improvements on those metrics. This is where chinese chip designers are in trouble: Taiwan has the foundries with the best silicium process, and now you get US restrictions on EU EUV tools. Even though I wish intel and amd to switch to risc-v in the not to far away future, I would give attention at the people over there who would try to torpedo RISC-V. The other one, ARM, well, they will try everything to sabotage it, RISC-V is a death sentence for them... unless they clearly move to RISC-V ultra performant micro-arch design. |
RISC-V likely has a future in mobile devices as it crawls up the performance tree like ARM did. This leaves ARM in a tight squeeze between x86 on the top and RISC-V on the bottom.