[0xcde4c3db]

> Modern, high end FPGAs have a feature known as Raw SerDes, which in essence allows you to bypass a PCIe or Ethernet controller and use those lanes (yes, PCIe lanes) to your heart's desire ...provided you can design a working communication protocol. Difficult, but not impossible by any means.

Not even close to impossible. I've recently been trying to figure out a relatively "low-tech" way of talking to modern displays that doesn't involve feeding VGA into a black-box ADC, and from what I've gathered so far, most of the serial link standards developed in the past ~25 years are basically overclocked Fibre Channel with the serial numbers filed off and most of the reliability/ordering guarantees quietly dumped in a roadside ditch.

[throwaway2037]

> most of the serial link standards developed in the past ~25 years are basically overclocked Fibre Channel

Fascinating. Do you have a blog post about this?

[mips_r4300i]

What he means is that almost all serial interfaces at the PHY layer are derivatives of FC's 8b/10b coding. You turn bytes into symbols and optionally apply some whitening with an LFSR. Much like a radio TX. Then some additional tricks like de-emphasis where you try and overdue the high/low transitions to compensate for your PCB substrate or cabling being cheap.

PCI express, SATA, usb3, HDMI (in a slightly different way), display port, etc etc. all use some form of 8b10b coding (or more efficient coding) with multi-gigabit serial transceivers.

In fact the PHY layer for USB3, PCIe 2.0 and SATA is identical - Intel designed a physical standard to encompass all three of those called PIPE. Nowadays that only exists as a virtual bus between silicon IP blocks.

[0xcde4c3db]

Right. And not only is the general approach the same (which one could credibly blame on a sort of "parallel evolution" driven by the changing economics of transistors vs. pins in chip manufacturing), but in some cases the relevant standards literally incorporate parts of Fibre Channel by reference. It was seeing the DisplayPort spec cite the ANSI Fibre Channel PHY standard to define its specific 8b10b code (there have been several, due to the inherent redundancy of that type of code; cf. the choice of the 2 "extra" symbols in base64) that started me down the rabbit hole.

[wtallis]

I'm not sure how many similarities there are between current mainstream interfaces and Fibre Channel specifically, but there has been an obvious trend of convergence, and Fibre Channel was probably one of the earliest instances. Nowadays, almost all high-speed interfaces have abandoned parallel links in favor of serial signalling over differential pairs implementing a packet-switched network. There's enough similarity at the physical layer that you'll often see a chip designer go with a general-purpose PHY shared across SATA/SAS, USB, and PCIe ports because they all operate at similar speeds and often similar encodings (eg. 8b10b). Likewise for sharing between InfiniBand and Ethernet.

DRAM is still almost always a traditional parallel bus, and it's basically alone in that. HDMI was a late holdout where the signalling was serial on differential pairs but the clock speed was variable depending on the data rate; newer versions of the standard rely instead on the link operating at one of a handful of fixed standard data rates, as done by everything else.