[mips_r4300i]

What he means is that almost all serial interfaces at the PHY layer are derivatives of FC's 8b/10b coding. You turn bytes into symbols and optionally apply some whitening with an LFSR. Much like a radio TX. Then some additional tricks like de-emphasis where you try and overdue the high/low transitions to compensate for your PCB substrate or cabling being cheap.

PCI express, SATA, usb3, HDMI (in a slightly different way), display port, etc etc. all use some form of 8b10b coding (or more efficient coding) with multi-gigabit serial transceivers.

In fact the PHY layer for USB3, PCIe 2.0 and SATA is identical - Intel designed a physical standard to encompass all three of those called PIPE. Nowadays that only exists as a virtual bus between silicon IP blocks.

[0xcde4c3db]

Right. And not only is the general approach the same (which one could credibly blame on a sort of "parallel evolution" driven by the changing economics of transistors vs. pins in chip manufacturing), but in some cases the relevant standards literally incorporate parts of Fibre Channel by reference. It was seeing the DisplayPort spec cite the ANSI Fibre Channel PHY standard to define its specific 8b10b code (there have been several, due to the inherent redundancy of that type of code; cf. the choice of the 2 "extra" symbols in base64) that started me down the rabbit hole.