[christiaanb]

One of the original authors of Clash here.

I was always torn on how to describe Clash to an audience whose background I don’t know up front: is it a hardware description ‘language’, or, is it a set of tools, libraries and scaffolding to use Haskell as a method for circuit description?

So yes, Clash is just Haskell. Although it is Haskell with certain GHC language extensions enabled by default plus a type-checking plugin for reasoning about type-level natural numbers.

That’s because the Clash compiler can only translate a semantic subset of Haskell to circuits. We use types to determine how big the circuit will become (fixed-length lists, fixed-depth trees, fixed-width numerics, etc.). So the semantic subset part means that Clash will not translate Haskell programs where the recursion depth is unknown at compile time, nor things like mutation (whether it’s ST or IO) or other I/O like actions.

Finally, why we’ve kept the “Clash is a functional hardware description language” is that unlike approaches such as nMigen, Chisel, Spinal, the Clash compiler translates the actual Haskell source code to VHDL/(System)Verilog. It uses the GHC Haskell compiler to do all the parsing, type-checking and “desugaring”. This means that with Clash you can use all of Haskell’s syntax to describe how the circuit operates, including if-expressions, case-expressions, etc. In the other approaches I mentioned you usually have to use some sort of ‘when’-function to describe run-time choice. So those approaches to me feel more like a “use-language-X-as-a-tool-for-circuit-description”, while Clash, again to me, does really feel more like a hardware description ‘language’.

[throwaway17_17]

I posted a comment on the main article, not realizing I’d left this tab open for 8 hours, so since you commented here I’ll ask the same question more briefly:

Does Clash compile to Verilog, as Chisel does, (your comment makes me think it does not)? Or is it that it goes directly to a net-list of transistors (I think that’s the right terminology).

[ymherklotz]

Clash compiles to Verilog or VHDL, just like most higher-level hardware description languages (Bluespec is another interesting one which has a Haskell-like dialect and the compiler is written in Haskell).

It's impractical for most new/independent hardware languages to go to some kind of netlist, because the components/modules you will have available will vary greatly depending on your final target. Depending on if you are going to target a specific Intel FPGA, Xilinx FPGA or even a custom ASIC with a specific cell library, the netlist will look very different, and even the tools translating from Verilog will look different.

As an aside though, Verilog is quite versatile, so you can actually represent a netlist in Verilog itself with custom cell libraries. Instead you refer to Verilog you normally write in as a register transfer level (RTL) description.

[throwaway17_17]

Thanks, I find hardware design interesting (despite a very small level of knowledge), so I’ll probably spend some of my lunch break chasing down links using RTL as a starting point.