[throwaway17_17]

I posted a comment on the main article, not realizing I’d left this tab open for 8 hours, so since you commented here I’ll ask the same question more briefly:

Does Clash compile to Verilog, as Chisel does, (your comment makes me think it does not)? Or is it that it goes directly to a net-list of transistors (I think that’s the right terminology).

[ymherklotz]

Clash compiles to Verilog or VHDL, just like most higher-level hardware description languages (Bluespec is another interesting one which has a Haskell-like dialect and the compiler is written in Haskell).

It's impractical for most new/independent hardware languages to go to some kind of netlist, because the components/modules you will have available will vary greatly depending on your final target. Depending on if you are going to target a specific Intel FPGA, Xilinx FPGA or even a custom ASIC with a specific cell library, the netlist will look very different, and even the tools translating from Verilog will look different.

As an aside though, Verilog is quite versatile, so you can actually represent a netlist in Verilog itself with custom cell libraries. Instead you refer to Verilog you normally write in as a register transfer level (RTL) description.

[throwaway17_17]

Thanks, I find hardware design interesting (despite a very small level of knowledge), so I’ll probably spend some of my lunch break chasing down links using RTL as a starting point.