[mattclarkdotnet]

Even at 1GHz, a trillion (10^12) writes is only 1000 seconds of work for a modern CPU. OK latency is a thing, so multiply by 10 and it takes a day. This is for DRAM where cells are individually addressed. For flash with wear levelling the numbers of course get bigger.

[jandrese]

In practice a memory location being written to that heavily will never escape the cache unless you are doing something exceptionally weird.

[DoctorOetker]

doesn't C have keywords like volatile to insist reading from RAM?

[aidenn0]

Volatile requires it emit instructions that access the object. So if the object is in RAMA, it will emit memory access instructions. However, on modern CPUs, that will still hit the cache. You need to either map in the memory as uncached, or flush the caches to force a memory access

[pbalcer]

no, that won't work. You'd have to clflush after every store. And even then, the cacheline might only ever get to the write pending queue (wpq) - and that you can't control.

[vlovich123]

I would seriously doubt there’s many instances of writing to a single volatile memory location at 1ghz (excluding benchmarks).

[pezezin]

Modern DRAM doesn't address individual cells. For both DDR4 and DDR5 the minimum burst length is 64 bytes, the width of a cache line of most CPUs.