[xw3099]

The barrier to automatic placement and route at the PCB level is not the algorithms. It the time it takes the user to create the routing constraints on the nets. For PCBs with less than, say, 100 nets. It's probably not worth it. You could wire it up manually faster than you could write and debug a constraints file.

That why for commercial PCB packages with support designs with 1000s of nets, such as Cadence's Allegro, one does see support for automatic routing of PCBs. And it's quite good.

[dragontamer]

I'm looking into maybe doing a BGA / MPU through KiCAD soon. Not that I'm confident in my abilities at all, but it'd be a challenge that I'd like to succeed in.

Yeah, you've listed off ~100 nets vs 1000s+ nets. But...

Many MPUs are BGA200 to BGA400 in size, and seemingly designed for 4-layer to 6-layer boards (available from OSHPark). Which means I expect around... maybe 200 nets or so in practice (a lot of the pins are either power-or-ground. But many other pins would be in fact connected to "something" and be their own net). More than your first number, less than your second number.

In your opinion, is that still within the feasibility of a hobbyist laying things out by hand? A lot of SiP MPUs have "internal DDR2" in sufficient quantities to boot Linux, although I'm also thinking about routing my own RAM for maximum flexibility.

[xw3099]

It’s definitely doable in one off quantities. And in fact people do it. Probably the most annoying thing would be dealing with length matching but honestly modern interfaces are much more tolerant than the specs imply. Power delivery could also be a sore point. So again, if you just looking to get a prototype working, it’s workable. But in volume. I wouldn’t go this route. This presentation lists some important things that are lacking in KiCAD when you really need to know the answer. https://archive.fosdem.org/2022/schedule/event/advanced_sim/...

[amelius]

I'm not sure what you are saying here. Would KiCad not benefit from these algorithms? What if the PCB has a lot of wide buses, etc? Why would someone using Allegro have different requirements than someone using KiCad?

Just trying to understand.

[xw3099]

It could definitely benefit. And if KiCAD wants to support larger systems then one might even argue they're required, eventually.

What I mean is not all nets are created equal. Is this an edge sensitive gpio or a level sensistive? Is this a net with a cap a current that's being integrated or edge rate control on a clock driver? A person knows because they can read the datasheets. The way for the algorithm to know is routing constraints, and their fairly tedious to write correctly which means for there to be good ROI on the time spent writing them, the algorithm needs to do a lot of work for you.

[amelius]

Ok, good point. Perhaps the role of each pad can be annotated in the symbol libraries. Or perhaps we can use LLM technology to read the datasheets and figure out the role of each net ;)