[amelius]

I'm not sure what you are saying here. Would KiCad not benefit from these algorithms? What if the PCB has a lot of wide buses, etc? Why would someone using Allegro have different requirements than someone using KiCad?

Just trying to understand.

[xw3099]

It could definitely benefit. And if KiCAD wants to support larger systems then one might even argue they're required, eventually.

What I mean is not all nets are created equal. Is this an edge sensitive gpio or a level sensistive? Is this a net with a cap a current that's being integrated or edge rate control on a clock driver? A person knows because they can read the datasheets. The way for the algorithm to know is routing constraints, and their fairly tedious to write correctly which means for there to be good ROI on the time spent writing them, the algorithm needs to do a lot of work for you.

[amelius]

Ok, good point. Perhaps the role of each pad can be annotated in the symbol libraries. Or perhaps we can use LLM technology to read the datasheets and figure out the role of each net ;)