[swetland]

Okay, so is there actual documentation for the SoC used on this critter? I mean a full Databook / Technical Reference Manual, not maybe 30 pages of overview, maybe a list of register base addresses (if you're lucky), and a pile of Linux kernel patches (upstream if you're lucky, but still of less value to someone wanting to actually write code for / port something to the SoC) or an "SDK" containing a bunch of low quality vendor code for the peripherals.

I'd love to see a RISC-V SoC (not just a dinky little MCU) that has real / complete documentation. So far I have yet to find any for any of the various RISC-V based SBCs that have shipped.

[kramerger]

This is a Wujian 600 from Alibaba (!). To my knowledge there is currently no publicly available documentation from the chip manufacturer.

Was the idea of an open ISA leading to an open SoC was just wishful thinking?

[pclmulqdq]

Not entirely, but the process is very slow.

RISC-V (and SiFive) caught a moment where it could be used is a way to squeeze ARM on pricing. It doesn't really meaningfully create openness on the interesting parts of the stack (core architecture, SoC architecture, etc.) on its own. In that sense, the hype is overblown.

It does _enable_ open-source cores to some degree, but that's it, someone has to take the leap to make a production-ready one. A few companies are trying, but an open-source SoC is even further down the road.

[brucehoult]

The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.

https://github.com/T-head-Semi/openc910

The same cores are used in the 64 core SG2042 workstation/server SoC.

[panick21_]

Open ISA is necessary but not sufficent. One step on a long journey.

[kramerger]

That is my point exactly.

RISC-V was sold to us as the fully open CPU ecosystem but all it offered was an open design and some reference implementation in Chisel. That is not much different from MIPS which opensourced some CPUs 10-15 years ago.

A lot more is needed for a fully open RISC-V computer.

[panick21_]

Nobody sold RISC-V as a fully open CPU or SOC ecosystem.

It simply allows for open source implementations to exists.

> but all it offered was an open design and some reference implementation in Chisel

You are confused between what RISC-V the foundation and what different people in the ecosystem do. RISC-V was started by Berkley and then they created a foundation. There are NO REFERENCE Implementation! Not in Chisel or anything else. Chisel is simply what Berkley used for some of their initial work.

And it has largely worked. There are lots of high quality open CPUs. This was certainty not the case in the past:

- https://www.openhwgroup.org/

- https://www.chipsalliance.org/

- https://opentitan.org/

There are many more.

> That is not much different from MIPS which opensourced some CPUs 10-15 years ago.

Its very different because you were not allowed to use those MIPS chips or built products with it. The only one that was as open was SPARC 32-bit.

What we don't have is cheap mass produced SoC that are well documented. But that a general problem of the industry not just RISC-V.

[MisterTea]

The link they liisted to the SoC is also broken: https://t-head.cn/TBD

[vaxman]

oh damn, I was about to go hard on an order bc I liked their location and the story. But I need more Chinese fabricated SoCs (which in 2023 are likely are pre-infected) like I need a hole in the head. I’ve seen quite a few crowds wind up in the garbage heap of history because “errbody is doing it” so forgive me while I plug my ears and scream the word No over and over again while I laugh at dem downvotin’ downvoters dat love cheap Chinese fabricated SoCs.

[imtringued]

>Was the idea of an open ISA leading to an open SoC was just wishful thinking?

The boot process for RISC V is standardised. There are going to be far more RISC-V SBCs that support uefi than ARM SBCs.

[kramerger]

The boot sequence is standardised on all CPU architectures. But is the boot firmware (and specially the M-mode fw) open on all devices?

ARM addressed this by creating ATF which most companies now use:

https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/

[0xTJ]

That's my biggest problem with personally enjoying RISC-V. I'd love to play with an application-class RISC-V processor, writing an OS for it and the like, but I'm waiting on a chip that's publicly well-documented in English.

[apricot]

If I had to wait for documentation in my native language, I would never work on any modern chips, period.

[snvzz]

The more mature VisionFive 2 and its SoC, JH7110, have some documentation[0].

I find the most useful there is the JH7110 TRM specifically.

There's links to a bunch more over here[1].

0. https://doc-en.rvspace.org/

1. https://forum.rvspace.org/t/visionfive-2-faq-quick-links/137...

[yuumei]

Agreed, the best I have found so far is the SiFive Unmatched: https://www.sifive.com/boards/hifive-unmatched which is a full mini-itx motherboard. It's not a SoC though.

As far as I can see, the only thing that isn't documented is the DDR startup/training code, which is a binary blob in u-boot. There are a few registers that are undocumented which need to be set to start up but I think the rest is well documented.

[swetland]

SiFive has pretty good documentation for their cores and chips -- they are more PC/Server class (some lowspeed peripherals plus PCIE and Ethernet) than SoC style. The databook does not have register level docs for PCIE and Ethernet but both look like off-the-shelf IP (hopefully documented somewhere -- I haven't investigated) but otherwise seems pretty thorough.

https://www.sifive.com/documentation

In addition to a documented RV64 SoC, it'd be cool to see some RV32 MCUs that are a little beefier -- more competitive with the mid-range Cortex M4 and M7 stuff (more peripherals, more SRAM, etc) -- instead of the existing stuff that looks similar to very tiny M0/M3 devices.

[snvzz]

The more mature VisionFive 2 and its SoC, JH7110, have some documentation[0].

I find the most useful there is the JH7110 TRM specifically.

There's links to a bunch more over here[1].

0. https://doc-en.rvspace.org/

1. https://forum.rvspace.org/t/visionfive-2-faq-quick-links/137...

[MisterTea]

In addition to all that, is the GPU documented? Clicking "Request technical specs" on the Imagination website brings me to a page asking me for my business name, business email, business...

[2Gkashmiri]

Haha.

Last time I wanted rs-232 specs of a solar inverter, took me months to contact them and after some persuasion, a guy emailed me an NDA I had to physically print, sign, scan and send them back before they gave me a copy.

Obviously I was feeling funny so I signed Johnathan doe and they send me the file.

Turns out, that file was readily available online in forums because others had done the same thing.

So much for NDA. Sigh

[MisterTea]

I was looking at an import inverter that advertised CAN and rs485 support both on the website and in the manual's specs section with zero further mention. I emailed the vendor and the manufacturer at least 4 times requesting documentation with zero response. Seems to be status quo for cheap import junk. Meanwhile outback power systems offers protocol documentation in the form of manuals freely downloadable. Incredible stupidity.

[2Gkashmiri]

on the contrary, in my case it was phocos.com which seems to be germany based and sells in many countries so this isn't just your rando junk but they still insist on stupid stuff

[imtringued]

Imagination is trying to opensource their GPU drivers.

[snvzz]

To be more exact, they've contracted the services of a third party company to write a new mesa3d driver.

Their proprietary driver will stay closed, but hopefully they'll be able to deprecate it at some point.