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by kramerger 1070 days ago
This is a Wujian 600 from Alibaba (!). To my knowledge there is currently no publicly available documentation from the chip manufacturer.

Was the idea of an open ISA leading to an open SoC was just wishful thinking?

5 comments

Not entirely, but the process is very slow.

RISC-V (and SiFive) caught a moment where it could be used is a way to squeeze ARM on pricing. It doesn't really meaningfully create openness on the interesting parts of the stack (core architecture, SoC architecture, etc.) on its own. In that sense, the hype is overblown.

It does _enable_ open-source cores to some degree, but that's it, someone has to take the leap to make a production-ready one. A few companies are trying, but an open-source SoC is even further down the road.

The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.

https://github.com/T-head-Semi/openc910

The same cores are used in the 64 core SG2042 workstation/server SoC.

Open ISA is necessary but not sufficent. One step on a long journey.
That is my point exactly.

RISC-V was sold to us as the fully open CPU ecosystem but all it offered was an open design and some reference implementation in Chisel. That is not much different from MIPS which opensourced some CPUs 10-15 years ago.

A lot more is needed for a fully open RISC-V computer.

Nobody sold RISC-V as a fully open CPU or SOC ecosystem.

It simply allows for open source implementations to exists.

> but all it offered was an open design and some reference implementation in Chisel

You are confused between what RISC-V the foundation and what different people in the ecosystem do. RISC-V was started by Berkley and then they created a foundation. There are NO REFERENCE Implementation! Not in Chisel or anything else. Chisel is simply what Berkley used for some of their initial work.

And it has largely worked. There are lots of high quality open CPUs. This was certainty not the case in the past:

- https://www.openhwgroup.org/

- https://www.chipsalliance.org/

- https://opentitan.org/

There are many more.

> That is not much different from MIPS which opensourced some CPUs 10-15 years ago.

Its very different because you were not allowed to use those MIPS chips or built products with it. The only one that was as open was SPARC 32-bit.

What we don't have is cheap mass produced SoC that are well documented. But that a general problem of the industry not just RISC-V.

The link they liisted to the SoC is also broken: https://t-head.cn/TBD
oh damn, I was about to go hard on an order bc I liked their location and the story. But I need more Chinese fabricated SoCs (which in 2023 are likely are pre-infected) like I need a hole in the head. I’ve seen quite a few crowds wind up in the garbage heap of history because “errbody is doing it” so forgive me while I plug my ears and scream the word No over and over again while I laugh at dem downvotin’ downvoters dat love cheap Chinese fabricated SoCs.
>Was the idea of an open ISA leading to an open SoC was just wishful thinking?

The boot process for RISC V is standardised. There are going to be far more RISC-V SBCs that support uefi than ARM SBCs.

The boot sequence is standardised on all CPU architectures. But is the boot firmware (and specially the M-mode fw) open on all devices?

ARM addressed this by creating ATF which most companies now use:

https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/