[maximusdrex]

> I just can't express my architecture in such an abstract form whose logic-level simulations (without considering delays, area, routing, power and clock rate) will give a clear indication of win.

Why not? There are plenty of open source RISC-V soft CPUs available for you to run on the same FPGA to benchmark against. If its the architecture which is special it doesn't matter if it competes against top of the line chips, just that it beats out everything comparable. You don't need to prove that your design will beat out a similarly designed chip on advanced silicon, just that your design implemented in the slow FPGA is better at something (not necessarily everything) than a CPU trying to emulate the same behavior. Having the PDKs won't help you much either, since on top of that it will take hundreds of thousands of dollars (minimum) in software costs and teams of people to help fine-tune and simulate such a large design. Doing this without the intention to eventually tape-out that design is a massive waste of resources.

I understand where you're coming from but the point of getting access to those PDKs isn't for rapid prototyping. The value proposition of your design must already be clear before beginning to design for a specific process. If you can't prove that your design has significant advantages that no chip in the next few years can possibly compete with, then there's just no point in attempting to design, synthesize, and simulate it on advanced nodes. That process is a significant investment in itself and if you're unsure enough about the potential benefits that you need to know exactly what it would look like in reality, then it's just too risky to spend the years it will take to get a working chip which may already be outclassed by the time your first chips come off of the line.

> Sure, but I specifically want to research the optimal intermediate point between classical CPU architectures and classical FPGA architectures.

That sounds cool, but this makes it sound like you're a really long way off from considering the specific characteristics of a given process node. Focus on designing an architecture which does something better than current designs can possibly do, such that the value of implementing it in a chip will be unquestionable.

[chromoblob]

Without PDK, how to prototype at all? My prototype will be so out of touch with actual reality of process parameters that it will have no value. Even if it outperforms soft CPUs, I will have to redesign from scratch at the point I will get actual PDK, since my business is not creating soft CPUs. Also how do you define "comparable" for a logic-level design? I don't get how such a metric stays useful when is tried to be used for measuring actual physical designs.

> You don't need to prove that your design will beat out a similarly designed chip on advanced silicon, just that your design implemented in the slow FPGA is better at something (not necessarily everything) than a CPU trying to emulate the same behavior.

No, I do. Since, again, my objective is creating actual chip, not a soft processor.

Fine-tuning will come only after it's clear that the design is good.

I just don't see a way to create such an abstract model which will have any utility for measurement.

And the advantages depend on actual implementation, which depends on process parameters, and if I try to make a design which is good regardless of actual parameters, this will be too conservative and I may not succeed.