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by renox 1105 days ago
Even a very low penalty isn't something that the industry is willing to produce..

For example, the RISC-V is derived from the MIPS, the MIPS had some instruction to trap on integer overflow, it's a very minor penalty to have these instructions, and guess what? They haven't been included in RISC-V..
1 comments
snvzz 1105 days ago
RISC-V would not add instructions w/o a strong justification, as simplicity has value in itself, and RISC-V is very RISC in recognizing that.

If it's not that frequent and it can be done with 2 instructions, it'd be quite hard to make the argument for a dedicated instruction.

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renox 1104 days ago
Except that as soon as you have two instructions instead of one, people starts talking about cache pressure and turns off the safety. Optional security == no security.
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snvzz 1104 days ago
By that same logic, you might as well run everything in M mode.
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