[nuc1e0n]

So my takeaway from this article is this: RISC largely displaced CISC except in legacy situations as you could get better throughput for the same number of transistors by moving work into the compiler. In turn Out-of-Order execution largely displaced RISC as you could get better throughput for the same number of transistors by moving more work into the compiler.

How else might processor topology design dogma be hindering the performance we could get by having better compilers? This is especially important now the transistor budget isn't nearly so flexible.

[thethirdone]

> In turn Out-of-Order execution largely displaced RISC as you could get better throughput for the same number of transistors by moving more work into the compiler.

What work does OoO execution displace to the compiler? I thought that OoO CPUs get better performance on the exact same programs compared to in order CPUs.

[nuc1e0n]

Ensuring register accesses are interleaved in a good way right?

[thethirdone]

Register renaming allows CPUs to eliminate stalls due to reuse of a register; I have not noticed any compiler putting particular emphasis on interleaving accesses well.

That is actually more of a problem on in order CPUs because a single stall will hold up the entire CPU instead of take longer to commit while other stuff is going on.

[nuc1e0n]

So if compilers did this better then processors wouldn't need the extra complexity and the transistors needed to support it themselves?