[memetomancer]

Perhaps you are unaware of the angstrom scale process nodes on the semiconductor roadmaps? i.e., IMEC, TSMC and Intel all aggressively pursuing "20A" at the moment with an eye toward a new generation of sub-1n production.

This isn't just some arbitrary guesswork on a blog, it's practical planning by the major suppliers. Check it out.

[Schroedingersat]

Please don't be condescending and wrong at the same time. The quantum tunnelling limit didn't mysteriously go away because the marketing department decided to name things based on the thickness of one particular feature. Nor do the laws of physics change when you bury your transistor in dialectric (the wavelength does, but that only works once).

Node name just barely correlates with minimum feature size (how thin can a line be drawn). That's starting to break down (hence intel 7 and 2N and so on) but that's not the limit I'm speaking of. The "2nm" nodes wind up with functional units about 30nm from center to center.

Compare to the 22nm node which was almost precisely 44nm center to center for a dram cell. In density terms there's maybe a factor of ~20 between 22nm and 2nm processes, so functionally the 2nm node can make things which are about a fifth the linear dimension.

Gate pitch has a fairly hard limit based on voltage and electron wavelength.

You're never going to put another transistor within about 2nm of a first one and have them both work. Hence the roughly order of magnitude in linear dimension past current.

[memetomancer]

I wasn't being condescending, and I am objectively not 'wrong'. I merely urged you to gather information you may not be familiar with. Particularly IMECs roadmap.

I will point out that you instantly went into condescending mode after complaining about my imagined condescension. I assure you, I'm well aware of what a process node implies about measurement of larger features. I'm also aware of the promising approaches coming down the pike.

I'm _also_ aware of the decades-old Internet tradition of people posting about the hard physical limits and immediate death of Moore's law, even as the limits are overcome year after year.

I am glad that you have a handle on the problems we face here, but please try to keep in mind that these challenges are a beginning, not an end.

[Schroedingersat]

You continue to he condescending and wrong. You urged me to look up marketing names as if they trumped reality when the relevant number was already in my comment.

Those predictions initially pointed directly to the 2020-2030 range, then the goal posts were moved to keep moores law alive (it's not a doubling every 18 months, it's 2 years). They point to 2040 now. If you stick to the 18 months rule under which the predictions based on the hard physical limits were made in 2000-2008 then it has already come true. Putting ever smaller numbers in the names of process nodes where the density of functional units is barely increasing does not change this.

Nehalim was noted for it's relatively large die area and low transistor count at about 2.7MTr/mm^2.

core2 on 45nm was about 3.8

Zen 4 is about 93.

93/2.7 is a factor of 36, 93/3.8 is 24. 2^7 is 128, 2^9 is 512.

Mobile processors are slightly better from a raw numbers POV, but already have a large portion of their area dedicated to tiled functional units like sram and gpu cores. Switching from a complex bespoke design to tiling only helps once. Even an m1 at 133MTr/mm^2 vs nehalim is only a factor of 48. These numbers are not even commensurable, because a much larger fraction of the transistors in the M1 do not do anything than in a core2

Prices per unit of die area are about stable although chiplets are needed (again) to maintain yield. This will go up with EUV and more exotic materials used to increase the dialectric constant.

Clocks are stable.

Performance per watt will continue to increase for a while after using architectural changes similar to some of those mentioned in TFA, but there is no getting around the second law with a classical computer.

[memetomancer]

Just out of curiosity, can you explain to me what you mean by 'marketing names' in relation to IMEC? I'm not quite convinced you understand what that organization is, what they do, or what they have accomplished.

[Schroedingersat]

The name at the top of the slide for a node which says '3NM' or '20A' and increasingly the 'transistor density'.

The former were divorced from a specific measurement of a functional unit at around 22nm to make press releases sound better and not scare investors when it became clear that Moore's law was dying, and the latter are increasingly divorced from a measurement relating to the density of actual functioning logic on the die.

The best bit is metal pitch and poly pitch are actually on those slides which would have allowed you to see what I meant if you'd read them and see that there's no roadmap past a functional unit roughly 10nm in linear dimension. That roadmap will likely be extended to somewhere in the 5-2nm range at some point, but after that, transistors are basically done because that's how big 'an electron in a low voltage potential well' is.

[jcranmer]

Note that the size label of process nodes is almost completely uncorrelated to actual feature size. GP makes the comment that the existing ~5-7nm nodes are actually running at ~30nm gate pitch.