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by ahmadmijot 1393 days ago
Are you the author? I've read the slides but can't find the details. What kind cell library this project use? I know from someone in the IC design industry said that it's kind of hard to access all the tools and semiconductor IPs without some kind of NDA or agreement with library vendors and foundry.
2 comments
q3k 1393 days ago
(Not the author, but in the know.)

This uses the Skywater 130 process. It’s backed by an open source PDK (SKY130B), and is going to be taped out via an Efabless shuttle, just like OpenMPW shuttles sponsored by Google.

The difference between this and a ‘plain’ OpenMPW shuttle is that this can fit a ton of tiny/toy/demo designs, enabling a lot of people to get their toes wet with ASIC design without having to take up a ‘large’ shuttle spot.

https://skywater-pdk.readthedocs.io/en/main/

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thrtythreeforty 1393 days ago
The Skywater shuttles are never full, to the best of my knowledge. However, it is a lot of work to get off the ground with the PDK (synthesis and physical design for chips is a totally separate set of skills on top of logic design), so if this further lowers the barrier to entry then that's fantastic
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rrss 1393 days ago
The last 3 or 4 openmpw shuttles have been full.
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thrtythreeforty 1393 days ago
That's great to hear, I'm glad to be corrected.
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jecel 1391 days ago
Actually, all of the open shuttles have been full with the last few oversubscribed by larger and larger margins (about 100% for MPW6 if I remember correctly).

It was the commercial shuttles, called ChipIgnite, that have had space left over.

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rrss 1390 days ago
I had in mind that OpenMPW-1 was not quite full, and looking now on efabless.com I see 37 projects submitted for MPW-1.

but i don’t think it really matters - there have been lots of submissions for all of them and a ton of cool stuff, and yeah the recent open shuttles are definitely full :)

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bajsejohannes 1393 days ago
I'm not the author, and honestly know very little about ASICs. But apparently enough to get a design onto this tapeout! :D

If q3k's answer wasn't sufficient, maybe you can find more answers in the github repo that builds everything? https://github.com/mattvenn/wokwi-verilog-gds-test

Otherwise, there's a discord where the author (Matt) very active: https://discord.gg/rPK2nSjxy8

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