[ralferoo]

Forgot to note, if you're really short of GPIO, you could also use two 8-line to 1-line data selector chip, e.g. 74151, so you'd have a 74138 to select one of 8 rows, and two 74138 which select a column each, and two further input pins to read from the result. That would reduce GPIO down to 8 (6 out, 2 in).

[ralferoo]

And just in case you're really really short of GPIO, you can use a 74595 shift register to feed the column and row selection, so you'd just need clock and data outputs.

You could also use 74251 8-to-1 multiplexer as that has an output enable, so you could use your remaining 2 outputs from the shift register to enable one of the two multiplexer chips. If you're not latching the outputs on the shift register, then you'd want a resistor between the two outputs so they don't fight.

So then, the ultimate reduction in GPIO would be to 3 lines - clock, data, in.

Obviously, for each of these, as you reduce the number of IO pins, you increase the time required to scan the matrix.

[joezydeco]

74595s are incredibly useful, compatible with SPI interfaces, and completely forgotten by today's engineers.

I have a current project where I needed to drive a large number of CS lines on a SPI bus. Others suggested I/O expanders and even - good lord - an entire M0 controller to handle it. I solved it with a bitbanged chain of 74HC595s, under $1 in BOM cost.