It would be a significant amount of work. The MiSTer project is specifically targeted at the DE10-Nano so it's designed for that FPGA and that peripheral set. In particular MiSTer relies on the onboard arm to run support software, you'd need to replace that on this (perhaps with a RISC-V softcore you could build the MiSTer software for but lots of software work to do to make that work).
It may also simply not be possible. The DE10-Nano has DDR memory for example but most MiSTer cores need extra add-on SDRAM. The reason being the latency on the DDR is just too high for the accurate emulate most cores are aiming for. So SDRAM is required. On this board you don't have that option. Though perhaps you can build your own DDR controller, with the DE10-Nano you have to use the hard controller built into the FPGA. Perhaps another controller specifically optimised for the latency needs of MiSTer cores could work. Each core would need potentially significant porting work to use this new setup as they get direct access to the SDRAM pins in MiSTer. You'd need to trace back to where they're actually generating memory accesses and then plug that into whatever new DDR controller you had.
There's also a small amount of IO pins on a high density header. I built an adapter that converts the LVDS voltage levels to TMDS so you can use it with HDMI or DVI - https://github.com/teknoman117/ACORN-CLE-DVI
Side note - this is the smallest pitch component I've ever soldered. Used a stencil and a hotplate since these are 0.4mm QFNs.
Edit - I really need to update the pictures. I forgot to twist the differential pairs before taking them.
The PCIe link definitely has plenty of bandwidth to stream uncompressed video to the host system—and if that host supports P2P DMA, it's probably even possible to push straight to VRAM without a round-trip through the host CPU's RAM. If there's enough room left on the FPGA, it could implement upscaling and CRT-emulating filters to provide a 4k stream to the host.
The downside is that you'd need custom drivers and software on the host system to redirect input events to the FPGA and handle the video feed it produces.
It may also simply not be possible. The DE10-Nano has DDR memory for example but most MiSTer cores need extra add-on SDRAM. The reason being the latency on the DDR is just too high for the accurate emulate most cores are aiming for. So SDRAM is required. On this board you don't have that option. Though perhaps you can build your own DDR controller, with the DE10-Nano you have to use the hard controller built into the FPGA. Perhaps another controller specifically optimised for the latency needs of MiSTer cores could work. Each core would need potentially significant porting work to use this new setup as they get direct access to the SDRAM pins in MiSTer. You'd need to trace back to where they're actually generating memory accesses and then plug that into whatever new DDR controller you had.