[gchadwick]

It would be a significant amount of work. The MiSTer project is specifically targeted at the DE10-Nano so it's designed for that FPGA and that peripheral set. In particular MiSTer relies on the onboard arm to run support software, you'd need to replace that on this (perhaps with a RISC-V softcore you could build the MiSTer software for but lots of software work to do to make that work).

It may also simply not be possible. The DE10-Nano has DDR memory for example but most MiSTer cores need extra add-on SDRAM. The reason being the latency on the DDR is just too high for the accurate emulate most cores are aiming for. So SDRAM is required. On this board you don't have that option. Though perhaps you can build your own DDR controller, with the DE10-Nano you have to use the hard controller built into the FPGA. Perhaps another controller specifically optimised for the latency needs of MiSTer cores could work. Each core would need potentially significant porting work to use this new setup as they get direct access to the SDRAM pins in MiSTer. You'd need to trace back to where they're actually generating memory accesses and then plug that into whatever new DDR controller you had.