The ISA wasn't that bad, but the weak memory-ordering model was a huge pain in the ass. I worked for a while with some of the Alpha folks years later, and they did a lot of really great work, but they did bring that weak memory model along with them. It allowed us to find many Linux kernel bugs that had lain dormant since Alpha because nothing since had repeated the mistake. Fun times ... not.
"According to Allen Baum, the StrongARM traces its history to attempts to make a low-power version of the DEC Alpha, which DEC's engineers quickly concluded was not possible."
The other major problem with the Alpha was the high license costs of DEC operating systems, which greatly helped put it in the grave.
Intel bought it from HP, stripped it for parts, then killed it.
HyperTransport and a few other things were essentially just copies of Alpha's stuff cleanroom implemented by ex-Alpha employees. Designs like Sandy Bridge look quite similar to EV8. QuickPath is just Alpha's interconnect with some updates (HyperTransport was also a cleanroom copy from ex-Alpha employees). Even AVX seems inspired by the 1048-bit SIMD planned for EV9/10.
I'd also add that a lot of excellent ex-Alpha engineers (e.g. Jim Keller, Dan Dobberpuhl off the top of my head) ended up designing great chips at other companies.
How did the Alpha ISA influence RISC-V, other than by its counterexample? Does RISC-V lack an integer divide? "Design of the RISC-V Instruction Set Architecture" mainly uses Alpha in the phrase "Unlike Alpha, ..." i.e. as a warning to future people. In fact, the author fairly well excoriates all of the historic RISC architectures for being myopically designed.
My impression is that Alpha's ISA was mostly fine except for the power draw, DEC just didn't have the R&D budget to keep up with Intel and all of the foundries and had their lunch eaten by x86 just like every other chip designer in the 80s and 90s.
Alpha was astonishing when it came out. It ran x86 code in emulation faster than any real x86 could go. Its only serious flaw was its chaotic memory bus operation ordering, which came to matter when you had two or more of them. Alpha died because DEC died, not the reverse.
x86, SPARC, Cell, EPIC, iAPX, i860, and even contemporary ARM versions are worse. If we reach into lesser-known ISAs or older ISAs, we could add a TON more to that list.