[Sprite_tm]

Can you elaborate that? For each BGA ball, I need one trace width of trace, plus one spacing width to the next trace, right? There's a space on the other side as well, but that's already 'provided' by the trace above.

Or do you mean if you want to connect to both the outer as well as the inner layer of balls? Then you'd be right I think, but that was not what I meant; I only calculated the spacing to connect to the outer layer and nothing more.

[fps-hero]

The best reference I can point to is the Xilinx bga pdf in google. Basically, for given capability (geometry really) there are only certain ways of breaking out pads. You can either fit multiple (luxury of process), one, or zero traces between vias and pads. And as a result of this, you need xTimes PCB layers to effectively breakout BGAs given there ball depth.

Simple chip scale bgas can be broken out one layer, but the geometry requires capabilities that only multi layer process provides.

The real takeaway is JLCPCB just got a whole lot more competitive with there 6 layer service. 0.2/0.4 vias, 0.1 trace/space is the holy grail. Anything smaller geometry than that you need board house support, and a finely tuned assembly process.