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by fps-hero
1550 days ago
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The best reference I can point to is the Xilinx bga pdf in google. Basically, for given capability (geometry really) there are only certain ways of breaking out pads. You can either fit multiple (luxury of process), one, or zero traces between vias and pads. And as a result of this, you need xTimes PCB layers to effectively breakout BGAs given there ball depth. Simple chip scale bgas can be broken out one layer, but the geometry requires capabilities that only multi layer process provides. The real takeaway is JLCPCB just got a whole lot more competitive with there 6 layer service. 0.2/0.4 vias, 0.1 trace/space is the holy grail. Anything smaller geometry than that you need board house support, and a finely tuned assembly process. |
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