[uluyol]

Cost increases super-linearly with size. One reason for this is defects: if a single defect ruins a whole chip, then for a constant number of defects per square inch, you'll get more usable square inches of silicon when you have small chips than big ones. Of course you can build chips that can tolerate a few defects, but the principle holds.

This is also why high quality TVs are harder to manufacture than high quality phone displays. You have a lot more waste when you need to throw out/recycle a TV screen compared to a phone screen. And both are considered bad when they have just one bad pixel.

[adtac]

>for a constant number of defects per square inch

Is this assumption true?

[Qub3d]

Its more the geometry of the process than the rate of failure. The post is just saying, "if the rate were constant". Basically, throw a dart at a wafer. Wherever the dart hits, the whole circuit/chip containing that point is now worthless. Assuming you threw the same number of darts (failures) at a board with a smaller chip, and a board with a large chip, the larger process wafer loses more total silicon (as a percentage of usable area).

With smaller chips, you have a smaller "grid" for your dart to land on. So the total number of failures (darts) being the same, you still end up with less usable silicon, since the bigger grid means you throw away a lot more surface area with a failure.

Take a look at this picture of a failure map, if you would like some visuals: https://ars.els-cdn.com/content/image/1-s2.0-S09521976120008...

[jboy55]

That image kind of looks like cosmic ray trails in a cloud chamber, I wonder if some of the defects are related.

[uluyol]

The point is that the amount of silicon that is wasted when there is a defect is amplified more with larger chips. That assumption was more for ease of explanation, but perhaps I could have explained better.

[neurostimulant]

Isn't this why AMD is going with chiplets design? No reason they can't manufacture even larger processor then, right?

[uluyol]

One of the reasons, yes. Another benefit of chiplets is mixing and matching chips made on different processes or from different manufacturers.

AMD uses an IO die manufactured on an older process at another manufacturer (14 or 16nm Global foundries) than their core chiplets (7nm TSMC). I think they even used the same IO die across multiple generations of EPYC/Ryzen, but I'm not sure.

[geranim0]

> a single defect ruins the whole chip

no. intel used to make extra cores for their 128 core cpus to account for the defects, and it was not rare to receive a cpu with more than 128 cores because it was a good one.

[uluyol]

See the next sentence: "Of course you can build chips that can tolerate a few defects, but the principle holds."